Mosfet on silicon-on-insulator with internal body contact

ABSTRACT

A semiconductor device is disclosed that includes a semiconductor-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A drain metal-semiconductor alloy contact is located on the upper portion of the deep drain region and abuts the drain extension region. A source metal-semiconductor alloy contact abuts the source extension region. The deep source region is located below and contacts a first portion of the source alloy contact. The deep source region is not located below and does not contact a second portion of the source alloy contact, such that the second portion of the source alloy contact is an internal body contact that directly contacts the semiconductor layer.

FIELD OF THE INVENTION

The present invention generally relates to the field of semiconductors,and more particularly relates to metal oxide semiconductor field effecttransistors (“MOSFETs”) with internal body contacts.

BACKGROUND OF THE INVENTION

A conventional radio frequency (“RF”) MOSFET produced on asilicon-on-insulator (“SOI”) substrate includes a body contact in orderto eliminate the floating body effect. While logic MOSFETs on an SOIsubstrate can tolerate the floating body effect, RF MOSFETs cannot doso, especially MOSFETs that are to be used for analog applications. Thisis because such RF MOSFETs need to be modeled very accurately, and thefloating body effect is difficult to model because it is not asteady-state effect. Furthermore, the floating body effect often inducesa kink in the drain current versus drain-source voltage (Id-Vds)characteristic. This degrades the linearity as well as the power gain ofthe transistor. Therefore, a body contact is provided for an RF MOSFETon an SOI substrate in order to give the transistor a body-tiedconfiguration. The external contact to the body ensures a stable bodypotential. However, this external body contact requires extra area, andmore specifically increases the perimeter of the drain-to-body junction.This increases the capacitance and reducing the achievable cut-offfrequency (fT) and maximum frequency (fmax).

SUMMARY OF THE INVENTION

A semiconductor device is disclosed. The semiconductor device includes asemiconductor-on-insulator substrate including a buried insulator layerand an overlying semiconductor layer. The semiconductor layer is dopedwith a dopant of a first conductivity type. A gate is located on thesemiconductor layer and includes a gate dielectric layer located on thesemiconductor layer and a gate conductor layer located on the gatedielectric layer. A source extension region and a drain extension regionare formed in the semiconductor layer. The source extension region andthe drain extension region contact the gate dielectric layer. The sourceextension region and the drain extension region are doped with a dopantof a second conductivity type. A deep drain region is formed in thesemiconductor layer. The deep drain region contacts the drain extensionregion and abuts the buried insulator layer. A deep source region isformed in the semiconductor layer. The deep source region contacts thesource extension region and abuts the buried insulator layer. The deepdrain region and the deep source region are doped with a dopant of thesecond conductivity type. A drain metal-semiconductor alloy contact islocated on the upper portion of the deep drain region and abutting thedrain extension region. A source metal-semiconductor alloy contact abutsthe source extension region. The deep source region is located below andcontacts a first portion of the source metal-semiconductor alloycontact. The deep source region is not located below and does notcontact a second portion of the source metal-semiconductor alloycontact, such that the second portion of the source metal-semiconductoralloy contact is an internal body contact that directly contacts thesemiconductor layer.

In another embodiment, an integrated circuit is disclosed. Theintegrated circuit includes a circuit supporting substrate including asemiconductor device. The semiconductor device comprises asemiconductor-on-insulator substrate including a buried insulator layerand an overlying semiconductor layer. The semiconductor layer is dopedwith a dopant of a first conductivity type. A gate is located on thesemiconductor layer and includes a gate dielectric layer located on thesemiconductor layer and a gate conductor layer located on the gatedielectric layer. A source extension region and a drain extension regionare formed in the semiconductor layer. The source extension region andthe drain extension region contact the gate dielectric layer. The sourceextension region and the drain extension region are doped with a dopantof a second conductivity type. A deep drain region is formed in thesemiconductor layer. The deep drain region contacts the drain extensionregion and abuts the buried insulator layer. A deep source region isformed in the semiconductor layer. The deep source region contacts thesource extension region and abuts the buried insulator layer. The deepdrain region and the deep source region are doped with a dopant of thesecond conductivity type. A drain metal-semiconductor alloy contact islocated on the upper portion of the deep drain region and abutting thedrain extension region. A source metal-semiconductor alloy contact abutsthe source extension region. The deep source region is located below andcontacts a first portion of the source metal-semiconductor alloycontact. The deep source region is not located below and does notcontact a second portion of the source metal-semiconductor alloycontact, such that the second portion of the source metal-semiconductoralloy contact is an internal body contact that directly contacts thesemiconductor layer.

In yet another embodiment, a method for fabricating a semiconductordevice is disclosed. The method includes forming asemiconductor-on-insulator substrate including a buried insulator layer.A semiconductor layer is formed over the semiconductor-on-insulatorsubstrate. The semiconductor layer is doped with a dopant of a firstconductivity type. A gate is formed on the semiconductor layer andincludes a gate dielectric layer located on the semiconductor layer anda gate conductor layer located on the gate dielectric layer. A sourceextension region and a drain extension region are formed in thesemiconductor layer. The source extension region and the drain extensionregion contact the gate dielectric layer. The source extension regionand the drain extension region are doped with a dopant of a secondconductivity type. A deep drain region is formed in the semiconductorlayer. The deep drain region contacts the drain extension region andabuts the buried insulator layer. A deep source region is formed in thesemiconductor layer. The deep source region contacts the sourceextension region and abuts the buried insulator layer. The deep drainregion and the deep source region are doped with a dopant of the secondconductivity type. A drain metal-semiconductor alloy contact is locatedon the upper portion of the deep drain region and abutting the drainextension region. A source metal-semiconductor alloy contact abuts thesource extension region. The deep source region is located below andcontacts a first portion of the source metal-semiconductor alloycontact. The deep source region is not located below and does notcontact a second portion of the source metal-semiconductor alloycontact, such that the second portion of the source metal-semiconductoralloy contact is an internal body contact that directly contacts thesemiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are cross-sectional views showing fabrication of a MOSFET onan SOI substrate according to one embodiment of the present invention;

FIG. 5 illustrates masks for deep source-drain implants according to oneembodiment of the present invention;

FIG. 6 illustrates conventional masks for deep source-drain implants;

FIG. 7 shows a top-down view of a MOSFET on an SOI substrate accordingto one embodiment of the present invention;

FIG. 8 shows a cross-sectional view of the MOSFET of FIG. 7 taken alongline A; and

FIG. 9 shows a cross-sectional view of the MOSFET of FIG. 7 taken alongline A′.

DETAILED DESCRIPTION

Preferred embodiments of the present invention will be described indetail hereinbelow with reference to the attached drawings.

Embodiments of the present invention utilize an internal body contactthat does not require extra area to improve the performance of a metaloxide semiconductor field effect transistor (“MOSFET”) on asilicon-on-insulator (“SOI”) substrate. This MOSFET overcomes theproblems discussed above because a body contact is provided withoutincreasing the junction area of the transistor, and without increasingthe capacitance of the MOSFET. Thus, the MOSFET can achieve higherspeeds, while still suppressing the floating body effect for goodlinearity.

More specifically, compared to a conventional MOSFET on an SOI substratewith a body contact, the MOSFET of the present invention eliminates thecapacitance penalty for providing the body contact, so as to increasespeed. Further, the area of the MOSFET of the present invention isreduced compared to the conventional body-contacted MOSFET. Compared toa conventional floating-body MOSFET on an SOI substrate, the MOSFET ofthe present invention exhibits improved linearity and lower outputconductance, which improves power gain. Additionally, the MOSFET of thepresent invention can be fabricated without any more mask layers than aconventional floating-body MOSFET. The internal body contact of theMOSFET of the present invention can be made solely through designchanges to the conventional process flow, without the need for anyadditional processing steps (such as angled implants or alternateamorphization species).

FIGS. 1-4 show fabrication of a MOSFET on an SOI substrate according toone embodiment of the present invention. As shown in FIG. 1, an SOIsubstrate 8 is provided. The SOI substrate 8 is formed by a handlesubstrate 10 (e.g., a silicon substrate), an overlying buried insulatorlayer 12 (e.g., an oxide layer), and an overlying semiconductor layer30. Shallow trench isolation regions 20 of a dielectric material areformed in the semiconductor layer 30. The shallow trench isolationregion 20 abuts the buried insulator layer 12 and laterally surrounds anactive region 31 in the semiconductor layer 30, so as to electricallyisolate the active region 31 from other portions of the semiconductorlayer 30 (e.g., other active regions).

In exemplary embodiments, the active region 31 comprises a singlecrystalline semiconductor material, such as silicon, germanium, asilicon-germanium alloy, a silicon-carbon alloy, asilicon-germanium-carbon alloy, gallium arsenide, indium arsenide,indium phosphide, a III-V compound semiconductor material, a II-VIcompound semiconductor material, or an organic semiconductor material.In this exemplary embodiment, the semiconductor material comprisessilicon. The active region 31 of this embodiment is doped with a dopantof a first conductivity type, such as a p-type dopant (e.g., boron,gallium, or indium) or an n-type dopant (e.g., phosphorus, arsenic, orantimony). The concentration of the dopant is from about 1.0×10¹⁵atoms/cm³ to about 1.0×10¹⁹ atoms/cm³. Non-electrical stress-generatingdopants, such as germanium and carbon may also be present. The activeregion 31 may also have a built-in biaxial stress in the plane of theactive region 31 (i.e., in the plane perpendicular to the direction ofthe top surface 19 of the active region 31.

As shown in FIG. 2, a gate dielectric 50 and a gate conductor 52 areformed on the active region 31. More specifically, a stack of a gatedielectric layer and a gate conductor layer are formed on the activeregion 31. This stack is then lithographically patterned and etched toform the gate dielectric 50 and the overlying gate conductor 52 in aportion of the active region 31 of the semiconductor layer 30.

The gate dielectric 50 of this embodiment comprises a conventionaldielectric material (such as silicon oxide, silicon nitride, siliconoxynitride, or a stack thereof) that is formed by thermal conversion ofa top portion of the active region 31 and/or by chemical vapordeposition (“CVD”). In alternative embodiments, the gate dielectric 50comprises a high-k dielectric material (such as hafnium oxide, zirconiumoxide, lanthanum oxide, aluminum oxide, titanium dioxide, strontiumtitanate, lanthanum aluminate, yttrium oxide, an alloy thereof, or asilicate thererof) that is formed in a known manner (such as by CVD,atomic layer deposition (“ALD”), molecular beam epitaxy (“MBE”), pulsedlaser deposition (“PLD”), liquid source misted chemical deposition(“LSMCD”), or physical vapor deposition (“PVD”)). The thickness of thegate dielectric layer is from about 1 nm to about 3 nm in exemplaryembodiment having a conventional dielectric material, and from about 2nm to about 6 nm in exemplary embodiment having a high-k dielectricmaterial, and may have an effective oxide thickness on the order of orless than 1 nm.

The gate conductor 52 comprises a semiconductor (e.g., polysilicon) gatelayer and/or a metal gate layer. In one embodiment in which of the gatedielectric 50 comprises a conventional dielectric material, the gateconductor 52 is a semiconductor gate layer and has a thickness fromabout 40 nm to about 200 nm. In one embodiment in which the gatedielectric comprises a high-k dielectric material, the gate conductor 52is a metal gate layer abutting the gate dielectric 50 and comprising aconductive refractory metal nitride (such as TaN, TiN, WN, TiAlN, TaCN,or an alloy thereof). The thickness of the metal gate layer in thisembodiment is from about 2 nm to about 100 nm, and preferably from about7 nm to about 50 nm. In another embodiment, the gate conductor 52comprises a stack of a metal gate layer and a semiconductor gate layer.

The length L of the gate conductor 52 of this embodiment is determinedby lithographic means, and is a lithographic minimum length (or a“critical dimension”). In some embodiments, a trimming etch is employedto reduce the length L of the gate conductor 52 to a length that is lessthan the lithographic minimum length.

As shown in FIG. 3, a first gate spacer layer 53 comprising a dielectricmaterial (such as silicon oxide) is then formed on the gate conductor 52and on the semiconductor layer 30. Alternatively, a reactive-ion etchprocess can be used to remove the dielectric material on top of the gateand on the semiconductor layer so as to form a gate spacer only on thesidewall of the gate conductor 52. Ion implantations are performed intothe semiconductor layer 30 employing the gate conductor 52 as animplantation mask in order to form a source extension region 134A and adrain extension region 134B that are self-aligned to the gate conductor52. The source extension region 134A and the drain extension region 134Bare formed in the semiconductor layer 30 at the same time. This ionimplantation to form the extension regions can be performed before orafter the formation of the first gate spacer layer 53, or alternativelyformation of the first gate spacer layer 53 can be omitted. If the ionimplantation follows formation of the first gate spacer layer 53, thevertical portions of the first gate spacer layer 53 on the sidewalls ofthe gate conductor 52 also serve as an implantation mask. Incomplementary MOSFET (CMOS) technologies which have both n-type MOSFETsand p-type MOSFETs, block masks are used to define where extensionimplants occur. In particular, one mask is used to open n-type MOSFETregions and block p-type MOSFET regions for ion implantation of n-typedopants in order to form source and drain extension regions in the ntype MOSFETs. Another mask, complementary to the first mask, is used toopen the p-type MOSFET regions and block n-type MOSFET regions for ionimplantation of p-type dopants in order to form source and drainextension regions in the p-type-MOSFETs.

The portion of the active region that is not implanted with dopant ionsduring the ion implantation constitutes the body 32 of the MOSFET andhas first conductivity type doping. The source extension region 134A andthe drain extension region 134B has a first depth d1 (e.g., from about 5nm to about 50 nm), and outer edges of these extension regions extendunder the gate dielectric 50. Thus, the source extension region 134A andthe drain extension region 134B both abut the gate dielectric 50 andhave a second conductivity type doping, which is the opposite the firstconductivity type doping. The source extension region 134A and the drainextension region 134B of this exemplary embodiment have a dopingconcentration from about 1.0×10¹⁹ atoms/cm³ to about 1.0×10²¹ atoms/cm³.In some embodiments, another ion implantation done at a tilted angle isthen performed to form halo regions under the source and drain extensionregions.

As shown in FIG. 4, a second gate spacer layer is deposited on the firstgate spacer layer 53, and then these two layers are etched (e.g., usingreactive ion etching) to form a gate spacer 55. This gate spacer 55comprises the combination of the first gate spacer layer portion 54 andthe second gate spacer layer portion 56. In exemplary embodiments, thesecond gate spacer layer portion 56 comprises a dielectric material thatis the same as or different than the dielectric material of the firstgate spacer layer portion 54. For example, in this embodiment the firstgate spacer layer portion 54 comprises silicon oxide and the second gatespacer layer portion 56 comprises silicon nitride. The dielectricmaterials for the first and second gate spacer layer portions mayinclude low-k dielectric materials. The portion of the first gate spacerlayer 53 outside the outer sidewalls of the second gate spacer layerportion 56 is removed during the reactive ion etching.

Thus, the gate spacer 55 laterally abuts the sidewalls of the gateconductor 52 and the gate dielectric 50, and abuts the source extensionregion 134A and the drain extension region 134B. In this embodiment, thethickness of the gate spacer 55, as measured laterally at the base ofthe gate spacer 55 from the sidewall of the gate conductor 52 abuttingthe spacer 55 to an outer edge of the gate spacer 55 adjoining eitherthe source extension region 134A or the drain extension region 134B, isfrom about 10 nm to about 100 nm, and preferably from about 20 nm toabout 80 nm. In alternative embodiments, the gate spacer 55 is formed byonly one or more than two gate spacer layers.

Next, deep source-drain implants are performed. More specifically, amask is first formed to define where the deep source-drain implants willoccur. FIG. 5 shows masks for deep source-drain implants according toone embodiment of the present invention. These masks include a firstmask 502 for defining the deep source-drain implants of a p-type MOSFETand a second mask 504 defining the deep source-drain implants of ann-type MOSFET. The mask layout in FIG. 5 is used for making an n-typeMOSFET (NFET) and a p-type-MOSFET (PFET). This is done for illustrationpurposes only and is not meant to limit the present invention. Inpractice, designs typically include multiple incidences of NFETs andPFETs, and can have any layout style.

The first mask 502 for a p-type MOSFET has a blocking region 506 wherethe deep source-drain implants are blocked and an open region 508 wherethe deep source-drain implants occur. Because the first mask 502 is forforming p-type MOSFETs, this mask blocks all of the area over the n-typedevice NFET along with the area over the p-type device PFET that is notto be implanted. Additionally, the blocking region 506 includes twoextensions 510 and 512 that extend into the open region 508. While inthis embodiment the additional block regions 510 and 512 are linked tothe bigger blocking region 506, this is not the case in all embodiments.For example, in an alternative embodiment, the additional block regions510 and 512 are ‘islands’ inside the open region 508.

The second mask 504 for an n-type MOSFET has a blocking region 518 wherethe deep source-drain implants are blocked and an open region 520 wherethe deep source-drain implants occur. Because the second mask 504 is forforming n-type MOSFETs, this mask blocks all of the area over the p-typedevice PFET. Additionally, the blocking region 518 includes twoadditional areas 514 and 516 in the open region 520 over the n-typedevice NFET.

The blocking regions 506 and 518 block the ions being implanted duringthe deep source-drain implants, while the open regions 508 and 520 allowthe ions to pass through for deep source-drain implantation. In thisembodiment of the present invention, the two extensions 510 and 512 ofthe blocking region 506 of the first mask 502 and the two additionalareas 514 and 516 of the blocking region 518 of the second mask 504 areadded to the design of these masks. This can be seen in a comparisonwith the conventional masks for deep source-drain implants shown in FIG.6.

The first conventional mask 602 for a p-type MOSFET has a blockingregion 606 where the deep source-drain implants are blocked, and an openregion 608 where the deep source-drain implants occur. Because this maskis for forming p-type MOSFETs, all of the area over the n-type deviceNFET is blocked while a substantially square or rectangular area overthe p-type device PFET is open so that it will be implanted. Similarly,the second conventional mask 604 for an n-type MOSFET has a blockingregion 610 where the deep source-drain implants are blocked, and an openregion 612 where the deep source-drain implants occur. Because this maskis for forming n-type MOSFETs, a substantially square or rectangulararea over the p-type device PFET is blocked while all of the area overthe n-type device NFET is open.

In the exemplary embodiment, the two extensions 510 and 512 of theblocking region 506 of the first mask 502 and the two additional areas514 and 516 of the blocking region 518 of the second mask 504 are madeto block the deep source-drain implant in a portion of the source regionof the MOSFET. After the deep source-drain implantation has beenperformed, the mask is removed in a conventional manner and a subsequentrapid thermal anneal (“RTA”) is performed (alternatively, millisecondlaser anneal or flash anneal can be used) to provide relatively deepdiffusions for the deep source and drain regions.

As shown in FIGS. 8 and 9, the deep-source drain implants form a deepsource region 806 and a deep drain region 808. Next, a source silicidecontact 802 and a drain silicide contact 804 are formed by metallizationof exposed semiconductor material. In particular, in this embodiment, ametal layer is deposited directly on the semiconductor layer 30 (such asby a blanket deposition). The metal layer comprises a metal capable offorming a metal-semiconductor alloy with the semiconductor material ofthe semiconductor layer 30 (such as tungsten, tantalum, titanium,cobalt, nickel, platinum, osmium, or an alloy thereof). A preferredthickness of the metal layer ranges from about 5 nm to about 50 nm, andmore preferably from about 10 nm to about 25 nm. In some embodiments, ametal nitride capping layer (e.g., containing a refractory metal nitridesuch as TaN, TiN, or OsN) is deposited over the metal layer.

An anneal is then performed so that the metal layer reacts with thesemiconductor material of the semiconductor layer 30 to form the sourcesilicide contact 802 directly over the deep source region 806 and thedrain silicide contact 804 directly over the deep drain region 808.

The resulting structure is shown in FIGS. 7-9. FIG. 7 shows a top-downview with two source regions S and two drain regions D separated by gateconductors G, FIG. 8 shows a cross-sectional view taken along line A ofFIG. 7, and FIG. 9 shows a cross-sectional view taken along line A′ ofFIG. 7. As shown in FIGS. 7 and 8, in one portion of the MOSFET thedeep-source drain implants are not blocked in the source and drainregions. Thus, in this portion of the device the deep source region 806underlies the source contact 802 and the deep drain region 808 underliesthe drain contact 804. Further, the deep source region 806 contacts thesource extension 134A and the deep drain region 808 contacts the drainextension 134B.

On the other hand, as shown in FIGS. 7 and 9, in another portion of theMOSFET the deep-source drain implants are not blocked in the drainregion but are blocked in the source region. The implants are blocked inthis portion of the source region by the extensions or additional areasof the blocking region of the masks used for deep source-drain implants.Thus, in this portion of the device the deep drain region 908 underliesthe drain contact 904 but there is no deep source region underlying thesource contact 902. Instead, the source contact 902 directly overlaysthe body 32 in this portion of the device. The deep drain region 908contacts the drain extension 134B while the source contact 902 contactsthe source extension 134A.

Thus, the deep source-drain implant is blocked at the ends of the sourceregions, so that at the ends of these regions (as shown by hatching inFIG. 7) there is no deep source region and the silicide of the sourcecontact directly contacts the body. In the remainder of the sourceregions, the deep source regions underlie the source contact. Further,in all of each drain region, the deep drain region underlies the draincontact.

This structure provides an internal body contact at the ends of thesource regions as shown in FIG. 9, while leaving the remainder of thesource regions unchanged as shown in FIG. 8. Because the internal bodycontact also contacts the source extension region, body contact is madewithout a capacitance penalty compared to a floating body device. At thesame time, there is only a small impact on the source resistance becausethe deep source implant underlies most of the source contact.Additionally, because the shallow source extension still directlyconnects the silicide contact to the area under the gate in the areawhere there is the internal body contact (i.e., where the silicidecontact directly contacts the body), there is no loss of electricaldevice width in the body contact area. Thus, there is still currentconduction in this area, so there is no loss of drive current due to thebody contact.

The present invention is not limited to having the internal body contactlocated at only the far end of each source region. For example, inanother embodiment there is additionally an internal body contact areaat the other end of each source region, as shown by areas 702 in FIG. 7.Thus, in this embodiment a region at each end of each source region hasan internal body contact. In another embodiment, this is furtherextended so that the deep source-drain implant is blocked in multipleregions of each source region to produce more body contacts. In yetanother embodiment, the deep source-drain implant is blocked in a largerarea at the end of each source region to produce a larger body contacts.In other embodiments, one or multiple such internal body contacts areprovided at any location along each source region. As the area of thesource region area that is used for internal body contact is increased,the control of the body potential is improved at the expense ofincreased source resistance. Preferably, only the area needed tomaintain good control of the body potential is used for internal bodycontact.

After the contact areas are formed, the device is completed in aconventional manner and electrically connections are made between thecontact areas and other devices so as to form an integrated circuit.

Accordingly, embodiments of the present invention provide a MOSFET on anSOI substrate with an internal body-tied configuration. The internalbody contact allows the junction area and capacitance of the MOSFET toremain the same, while suppressing the floating body effect for betterlinearity. Thus, the capacitance penalty for providing a body contact iseliminated, which increases the speed. At the same time, the area ofMOSFET is reduced compared to conventional body-contacted devices.Further, the MOSFET can be fabricated without any more mask layers thana conventional floating-body MOSFET. The internal body contact of theMOSFET is made solely through design changes to the conventional processflow, without the need for any additional processing steps.

The MOSFET of the present invention is particularly suited for use as anRF MOSFET. While the resulting MOSFET is asymmetric (i.e., the sourceand drain are not reversible), this is usually of no consequence for RFcircuits, because the source and drain contacts rarely, if ever, need tohave their polarity reversed in such circuits.

It should be noted that some of the features of the examples of thepresent invention may be used to advantage without the corresponding useof other features. As such, the foregoing description should beconsidered as merely illustrative of the principles, teachings, examplesand exemplary embodiments of the present invention, and not inlimitation thereof.

It should be understood that these embodiments are only examples of themany advantageous uses of the innovative teachings herein. In general,statements made in the specification of the present application do notnecessarily limit any of the various claimed inventions. Moreover, somestatements may apply to some inventive features but not to others. Ingeneral, unless otherwise indicated, singular elements may be in theplural and vice versa with no loss of generality.

The circuit as described above is part of the design for an integratedcircuit chip. The chip design is created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer transmitsthe resulting design by physical means (e.g., by providing a copy of thestorage medium storing the design) or electronically (e.g., through theInternet) to such entities, directly or indirectly. The stored design isthen converted into the appropriate format (e.g., GDSII) for thefabrication of photolithographic masks, which typically include multiplecopies of the chip design in question that are to be formed on a wafer.The photolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

The method as described above is used in the fabrication of integratedcircuit chips.

The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare chip, or in a packaged form. Inthe latter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboard,or other input device, and a central processor.

1. A semiconductor device comprising: a semiconductor-on-insulatorsubstrate including a buried insulator layer and an overlyingsemiconductor layer, the semiconductor layer being doped with a dopantof a first conductivity type; a gate located on the semiconductor layer,the gate including a gate dielectric layer located on the semiconductorlayer and a gate conductor layer located on the gate dielectric layer; asource extension region and a drain extension region in thesemiconductor layer, the source extension region and the drain extensionregion contacting the gate dielectric layer, the source extension regionand the drain extension region being doped with a dopant of a secondconductivity type, which is opposite the first conductivity type; a deepdrain region in the semiconductor layer, the deep drain regioncontacting the drain extension region and abutting the buried insulatorlayer; a deep source region in the semiconductor layer, the deep sourceregion contacting the source extension region and abutting the buriedinsulator layer, the deep drain region and the deep source region beingdoped with a dopant of the second conductivity type; a drainmetal-semiconductor alloy contact located on the upper portion of thedeep drain region and abutting the drain extension region; and a sourcemetal-semiconductor alloy contact abutting the source extension region,wherein the deep source region is located below and contacts a firstportion of the source metal-semiconductor alloy contact, and the deepsource region is not located below and does not contact a second portionof the source metal-semiconductor alloy contact, such that the secondportion of the source metal-semiconductor alloy contact is an internalbody contact that directly contacts the semiconductor layer.
 2. Thesemiconductor device of claim 1, wherein the source and drainmetal-semiconductor alloy contact comprise a metal silicide.
 3. Thesemiconductor device of claim 1, wherein the semiconductor layercomprises a shallow trench isolation region surrounding an active areacomprising silicon, and the source and drain extension regions and thedeep source and drain regions are all formed in the active area.
 4. Thesemiconductor device of claim 1, wherein the second portion is locatedat one end of the source metal-semiconductor alloy contact.
 5. Thesemiconductor device of claim 1, wherein the deep source region is notlocated below and does not contact a third portion of the sourcemetal-semiconductor alloy contact, such that the third portion of thesource metal-semiconductor alloy contact is an internal body contactthat directly contacts the semiconductor layer, and the first portionseparates the second portion from the third portion.
 6. Thesemiconductor device of claim 5, wherein the deep source region islocated below and contacts a fourth portion of the sourcemetal-semiconductor alloy contact, and the deep source region is notlocated below and does not contact a fifth portion of the sourcemetal-semiconductor alloy contact, such that the fifth portion of thesource metal-semiconductor alloy contact is an internal body contactthat directly contacts the semiconductor layer, and the fourth portionseparates the first portion from the fifth portion.
 7. An integratedcircuit comprising a circuit supporting substrate including asemiconductor device, the semiconductor device comprising: asemiconductor-on-insulator substrate including a buried insulator layerand an overlying semiconductor layer, the semiconductor layer beingdoped with a dopant of a first conductivity type; a gate located on thesemiconductor layer, the gate including a gate dielectric layer locatedon the semiconductor layer and a gate conductor layer located on thegate dielectric layer; a source extension region and a drain extensionregion in the semiconductor layer, the source extension region and thedrain extension region contacting the gate dielectric layer, the sourceextension region and the drain extension region being doped with adopant of a second conductivity type, which is opposite the firstconductivity type; a deep drain region in the semiconductor layer, thedeep drain region contacting the drain extension region and abutting theburied insulator layer; a deep source region in the semiconductor layer,the deep source region contacting the source extension region andabutting the buried insulator layer, the deep drain region and the deepsource region being doped with a dopant of the second conductivity type;a drain metal-semiconductor alloy contact located on the upper portionof the deep drain region and abutting the drain extension region; and asource metal-semiconductor alloy contact abutting the source extensionregion, wherein the deep source region is located below and contacts afirst portion of the source metal-semiconductor alloy contact, and thedeep source region is not located below and does not contact a secondportion of the source metal-semiconductor alloy contact, such that thesecond portion of the source metal-semiconductor alloy contact is aninternal body contact that directly contacts the semiconductor layer. 8.The integrated circuit of claim 7, wherein the source and drainmetal-semiconductor alloy contact comprise a metal silicide.
 9. Theintegrated circuit of claim 7, wherein the semiconductor layer comprisesa shallow trench isolation region surrounding an active area comprisingsilicon, and the source and drain extension regions and the deep sourceand drain regions are all formed in the active area.
 10. The integratedcircuit of claim 7, wherein the second portion is located at one end ofthe source metal-semiconductor alloy contact.
 11. The integrated circuitof claim 7, wherein the deep source region is not located below and doesnot contact a third portion of the source metal-semiconductor alloycontact, such that the third portion of the source metal-semiconductoralloy contact is an internal body contact that directly contacts thesemiconductor layer, and the first portion separates the second portionfrom the third portion.
 12. The integrated circuit of claim 11, whereinthe deep source region is located below and contacts a fourth portion ofthe source metal-semiconductor alloy contact, and the deep source regionis not located below and does not contact a fifth portion of the sourcemetal-semiconductor alloy contact, such that the fifth portion of thesource metal-semiconductor alloy contact is an internal body contactthat directly contacts the semiconductor layer, and the fourth portionseparates the first portion from the fifth portion.
 13. A method forfabricating a semiconductor device, the method comprising: providing asemiconductor-on-insulator substrate including a buried insulator layer;forming an semiconductor layer overlying the semiconductor-on-insulatorsubstrate, the semiconductor layer being doped with a dopant of a firstconductivity type; forming a gate located on the semiconductor layer,the gate including a gate dielectric layer located on the semiconductorlayer and a gate conductor layer located on the gate dielectric layer;forming a source extension region and a drain extension region in thesemiconductor layer, the source extension region and the drain extensionregion contacting the gate dielectric layer, the source extension regionand the drain extension region being doped with a dopant of a secondconductivity type, which is opposite the first conductivity type;forming a deep drain region in the semiconductor layer, the deep drainregion contacting the drain extension region and abutting the buriedinsulator layer; forming a deep source region in the semiconductorlayer, the deep source region contacting the source extension region andabutting the buried insulator layer, the deep drain region and the deepsource region being doped with a dopant of the second conductivity type;forming a drain metal-semiconductor alloy contact located on the upperportion of the deep drain region and abutting the drain extensionregion; and forming a source metal-semiconductor alloy contact abuttingthe source extension region, wherein the deep source region is formedbelow and contacts a first portion of the source metal-semiconductoralloy contact, and the deep source region is formed such that it is notlocated below and does not contact a second portion of the sourcemetal-semiconductor alloy contact, such that the second portion of thesource metal-semiconductor alloy contact is an internal body contactthat directly contacts the semiconductor layer.
 14. The method of claim13, wherein the source and drain metal-semiconductor alloy contactcomprise a metal silicide.
 15. The method of claim 13, wherein thesemiconductor layer comprises a shallow trench isolation regionsurrounding an active area comprising silicon, and the source and drainextension regions and the deep source and drain regions are all formedin the active area.
 16. The method of claim 13, wherein the secondportion is located at one end of the source metal-semiconductor alloycontact.
 17. The method of claim 13, wherein the deep source region isformed such that it is not located below and does not contact a thirdportion of the source metal-semiconductor alloy contact, such that thethird portion of the source metal-semiconductor alloy contact is aninternal body contact that directly contacts the semiconductor layer,and the first portion separates the second portion from the thirdportion.
 18. The method of claim 17, wherein the deep source region islocated below and contacts a fourth portion of the sourcemetal-semiconductor alloy contact, and the deep source region is notlocated below and does not contact a fifth portion of the sourcemetal-semiconductor alloy contact, such that the fifth portion of thesource metal-semiconductor alloy contact is an internal body contactthat directly contacts the semiconductor layer, and the fourth portionseparates the first portion from the fifth portion.